The present invention relates to computers and, more particularly, to cache management. A major objective of the present invention is to enhance computer performance by eliminating some writes back of useless data to main memory.
Much of modern progress is associated with advances in computer technology. A computer system typically includes memory for storing data and program instructions and a processor for manipulating data in accordance with the program instructions. A typical processor contains many devices fabricated together on an integrated circuit so that they can communicate with each other at very high speeds. While a small amount of memory can reside with a processor on an integrated circuit, main memory is typically external. Accordingly, memory accesses can be a performance limiter for computers. This is particularly true for technical applications, in which processors are often starved for data from memory.
Caches are memory devices that hold copies of recently accessed sections of memory so that a processor can read some data from the cache instead of from memory. Very fast caches can be built into the same integrated circuit that bears the processor or on external circuits that are more closely coupled to the processor than is main memory. On-chip caches tend to be the fastest but have the most limited capacity. Off-chip caches tend to be larger and slower, while still offering a great speed advantage relative to main-memory accesses.
Caches can be used to speed up not only read operations but also write operations. It takes much less time to write to a cache location than to a main-memory location. However, data written to a cache location must, in general, be written to main memory; otherwise, cache and memory will not match, i.e., they will be “incoherent”. Accordingly, some “write-through” caches copy data to main memory as soon as possible after it is written to cache.
However, other “write-back” (or “copy-back”) caches achieve some performance advantage by delaying writes back to main memory until they are necessary. In a write-through cache, each modification of a cache line results in a separate write back to main memory; in a write-back cache, any intervening modifications can be included in a single write back. For example, a write-back cache can delay write back of a line until it is about to be replaced to make room for more recently fetched data. In this case, only one write back is required regardless of the number of modifications applied to the cache line.
This write-back strategy reduces memory accesses and improves performance not only when multiple writes are performed on the same cache line, but also in other circumstances. For example, when an external device writes directly to memory, that data should not be overwritten by data in the cache. Accordingly, a device driver can issue a purge instruction (e.g., as provided for by the PA-Risc architecture developed by Hewlett-Packard Company) for cache lines that correspond to those memory sections to be written to by the device. The purged data is never written back, saving the corresponding memory accesses. While the foregoing cache strategies have provided performance improvements, further performance gains are desired.